Many applications require components such as microprocessors and memory devices that use high speed busses to communicate. The microprocessors and memory devices are often mounted on substrates such as printed circuit boards and use conductors or traces on multiple layers to route the high speed busses. Microprocessors can have internal operating frequencies which extend into the gigahertz frequency range. Printed circuit board busses have not been able to latch data at these rates. A number of techniques have been employed to improve the rate of data communication on these busses. In one approach, data can be bussed at a higher transfer rate than addresses if the data is sent with an implied address sequence using a burst mode. In another approach, source synchronous busses have been employed to improve the rate of data communication. These buses use clocking signals, called strobes, which are generated by the sending agent and which are transmitted along with the data and address information. Data is latched on both the rising and falling edge of a strobe while addresses are latched only on the rising or only on the falling edge of the strobe. This approach effectively increases the data rate by a factor of two over the fundamental buss frequency. In yet another approach, two strobes are used wherein the strobes are out of phase with each other by 90° and the data is latched on both the rising and falling edge of each strobe. This approach effectively increases the data rate by a factor of four.
At these high frequencies and high data transfer rates, it can become a difficult challenge to design printed circuit boards which support this high level of performance. For example, high frequency signals can be reflected by variations in the impedance of the traces which can degrade the quality of the signals being transmitted. Use of sharp turns when routing the traces can introduce parasitic capacitive and inductive effects which result in reflections. Capacitive and inductive cross-coupling can occur between signal traces routed in close proximity. When traces are routed to connect to a package, the traces typically are narrower and closer together in the vicinity of the package. This is generally referred to as necking down, and is herein defined to be the distance over which the narrower and closer traces are routed. The traces are required to neckdown in order to contact and/or navigate the array of vias when under or in the immediate area of packages used to mount the components on the printed circuit board. If the neckdown distance is considerable, such as when traces are routed under the length of the package, the undesirable effects such as capacitive and inductive cross-coupling can become significant.
A variety of packages which include direct attach and surface mount socket types are used to mount the components on the printed circuit boards. For high pin-count devices such as microprocessors, ball grid array and pin grid array packages have become popular package types since they allow for a high number of terminals on each package. The terminals can be located over the entire bottom surface or a substantial portion of the package and typically employ a terminal footprint having a rectangular shape. FIG. 1 illustrates a bottom view of an exemplary 256 pin ball grid array package 50 and illustrates the interconnect density of solder balls 52 within the terminal footprint. The center to center distance (i.e. pitch) between the solder balls 52 is very small thus creating routing challenges when routing traces to avoid vias and other traces as they traverse from package to package. Pin grid array packages are essentially the same as ball grid array packages except that the pin grid array packages are mounted to the printed circuit board by inserting pins that extend from the bottom surface of the package into corresponding sockets on, or through holes in, the printed circuit board. The ball grid array and pin grid array packages generally have multiple power, ground and signal terminals. The signal terminals include data terminals, address terminals, clock/strobe terminals, control terminals, and other signal terminals. Buses are used to interconnect the data, address and clock/strobe terminals of the various packages. For example, data and address buses may be used with a source-synchronous signaling technique to connect several microprocessors and/or memory devices on printed circuit boards.
To overcome the challenges of routing printed circuit boards which support high frequencies and high data transfer rates when using packages having high interconnect densities, it is desirable to shorten the length of each trace used for synchronous bus routing to minimize the overall propagation delay between packages. It is often desirable to keep the length of each synchronous bus the same between packages and the propagation delay of each individual routed trace is the same within each source synchronous group. It is also desirable to minimize neckdown distance and to avoid routing traces with sharp turns when routing the traces to interconnect the package vias.